DRAM cell having storage capacitor contact self-aligned to bit lines and word lines
US5994730A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1996 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Nov 21, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures. The exposed etch barrier layer (46) over the source region (18) is cleared and a storage capacitor is formed having a contact that extends into the contact hole to make contact with the source region (18).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.