Method for analyzing defects in a semiconductor
US5994913A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 1996 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Mar 20, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In order to verify whether defects generated when the manufacturing process is in progress results in the electric failures during the operation of the devices, and to verify which process the defects which cause electric failures are generated in, there is provided a method for analyzing defects in a semiconductor device, including the steps of: measuring the positions of physical defects generated in each process; converting the positions of said the physical defects into logic row/column address data; and comparing said logic row/column address data converted from positions of said physical defects with electric failure data which are measured after the overall processes are completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.