Variable delay cell with a self-biasing load
US5994939A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 1998 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Jan 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0231
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable delay cell with a self-biasing load suitable for the implementation of a voltage controlled oscillator and other functions. Because the invention employs current steering between symmetric loads and fully differential voltage control, it is very fast relative to conventional methods and has reduced jitter and improved power supply noise rejection. Additionally, since the load is self-biasing, the need to externally generate a bias current for the load is eliminated. This significantly simplifies design. Also as the load readily self biases in response to changes in the bias current of the biasing transistor, desirable functionalities can be achieved merely by appropriately changing the bias current into the biasing transistor. Notably, the slew rate of both the rising and falling edge can be controlled in this way. Because the load provides a fully differential output, noise immunity as well as a 50% duty cycle is readily achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.