Multiple graphics pipeline integration with a windowing system through the use of a high speed interconnect to the frame buffer
US5995121A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Oct 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/121
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved method of incorporating a high performance graphics device into a base graphics subsystem of a processor includes two pairs of interface chips. One pair of interface chips is used to transfer pixel data between a base graphics system and the high performance graphics device, while the second pair of interface chips is used to transfer commands between the graphics device and the base graphics system. One of the pair of interface chips that is used to transfer pixel data is coupled to a bus within the base graphics subsystem while the second one of the pair is coupled to the graphics device. With such an arrangement, a high speed interface allows for pixel data to be fed directly to the frame buffer of the graphics subsystem, enabling the windows that are rendered by two different graphics systems to share a frame buffer memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.