Bit line precharge circuit with reduced standby current
US5995431A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1998 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Jun 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is designed with a memory array (102) having a plurality of memory cells arranged in rows and columns (204, 206, 210, 212). The memory array has a plurality of bit line pairs (202, 208, 282, 284) with each bit line pair connected to a respective column of memory cells and a bit line reference terminal (254). A control circuit (700) produces a control signal, the control signal having a first voltage for a first time, a second voltage for a second time and a third voltage for a third time. A precharge circuit (350, 352) connects at least one bit line pair to the bit line reference terminal, responsive to the first voltage for the first time and the second voltage for the second time. The precharge circuit disconnects the at least one bit line pair from the bit line reference terminal, responsive to the third voltage for the third time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.