Synchronous semiconductor memory device capable of rapidly, highly precisely matching internal clock phase to external clock phase
US5995441A · kind A · utility
26Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1998 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Oct 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An initial delay control data decision circuit detects to which portion of a variable delay circuit a pulse signal of an external clock signal of one cycle is propagated for a predetermined period of time, to determine an initial value for delay control data. Depending on the initial value for delay control data, a delay locked loop circuit configured of the variable delay circuit, a phase comparator circuit, a shift logic circuit, a delay control data holding circuit, a variable constant current circuit and a voltage generating circuit controls phasing of internal and external clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.