Directional repeater physical assignment and connection for high-performance microprocessors
US5995735A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Jun 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved method for routing interconnect lines in a VLSI chip using repeaters. First, an optimal virtual assignment of the repeater locations is determined according to a suitable method. The "virtual" assignment is the ideal location irrespective of where logic blocks which could form a repeater cell might located. Next, repeaters are assigned to physical locations close to the optimal virtual locations. Finally, an optimal global routing is done using the physical locations of the repeaters. The optimal global routing revises the original global routing upon which the original optimal virtual assignment of repeaters was done. Preferably, blocks of circuitry and routing channels are identified first. Instead of simply routing the interconnect lines through the channels, a portion of the interconnect lines are routed through available spaces in the blocks themselves. This will reduce the number of turns required both through the channels and to reach a repeater. By routing through the blocks, repeaters can be placed at the entry or exit point on the block, eliminating the need for providing L or U-turns to a repeater from a channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.