System and method for the injection and cancellation of a bias voltage in an attenuated circuit
US5996100A · kind A · utility
2Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1997 |
| Grant date | Nov 30, 1999 |
| Priority date | — |
| Expiry date | Dec 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/14
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for injecting and canceling a bias voltage in an attenuated circuit is presented. The attenuated circuit is disposed within a tri-state logic-level measurement apparatus. The bias voltage is provided to ensure that when the measurement apparatus is floating, it floats at the tri-state voltage. In one embodiment, a summing network is connected to an attenuator, a first voltage generator which provides a bias voltage and a second voltage generator which provides a cancellation voltage. In another embodiment, a FET amplifier is provided in place of the summing network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.