Method of manufacturing dual-bank memory modules with shared capacitors
US5996880A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Apr 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself. Having capacitors on only one of the surfaces reduces the number of placement sequences required, reducing manufacturing cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.