Vacuum assisted underfill process and apparatus for semiconductor package fabrication
US5998242A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Oct 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01322
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip fabrication assembly and method including a semiconductor package having a packaging substrate and a semiconductor die. An active circuit surface of the semiconductor die is positioned adjacent to a contact surface of the packaging substrate such that a substantially thin gap is formed therebetween. A semi-rigid shroud device is provided which defines a vacuum chamber configured to extend around the gap to hermetically seal the gap within the vacuum chamber. A dispensing device is provided having an outlet end positioned proximate the gap in the vacuum chamber which is adapted to vacuum flow the bonding material between the electrical contacts in the gap, and between the active circuit surface and the contact surface. The absence of air and any other gases forms a substantially voidless underfill layer of bonding material in the gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.