Method to grow self-aligned silicon on a poly-gate, source and drain region
US5998286A · kind A · utility
5Cited by
10References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Mar 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.