Integrated CMOS circuit arrangement and method for the manufacture thereof

US5998807A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Bernhard Lustig · Munich, DE
• Herbert Schaefer · Herdorf, DE
• Martin Franosch · Munich, DE

Key dates

• Filing date: Sep 9, 1997
• Grant date: Dec 7, 1999
• Expiry date: Sep 9, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

Semiconductor islands respectively comprise at least a Si.sub.1-x Ge.sub.x layer and a distorted silicon layer that exhibits essentially the same lattice constant as the Si.sub.1-x Ge.sub.x layer are formed on an insulating layer that is located on a carrier plate. The semiconductor islands are preferably formed by selective epitaxy and comprise p-channel MOS transistors and/or n-channel MOS transistors.