Semiconductor-on-insulator field effect transistors with reduced floating body parasitics
US5998840A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Sep 4, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/91
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
SOI FETs include an electrically insulating substrate, a semiconductor region on the electrically insulating substrate, a field effect transistor having source, drain and channel regions in the semiconductor region and a metal silicide region between the electrically insulating substrate and the semiconductor region. The metal silicide region (e.g., TiSi.sub.2) forms non-rectifying junctions with the source and channel regions of the field effect transistor so that holes accumulated in the channel region (upon impact ionization) can be readily transported to the source region (and contact thereto) via the metal silicide layer and recombination of the holes with electrons in the source region can be carried out with high efficiency. The metal silicide region ohmically contacts the source and channel regions, but does not form a junction with the drain region of said field effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.