Architectures for programmable logic devices
US5999016A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Aug 28, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Each super-region may be like a small or moderately sized programmable logic device and may include a two-dimensional array of intersecting rows and columns of regions of programmable logic. Each region may in turn include a plurality of subregions of programmable logic. Horizontal and vertical inter-super-region interconnection conductors are associated with the rows and columns of super-regions. These conductors are selectively connectable to horizontal and vertical inter-region interconnection conductors in the super-regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.