Multiple phase synchronous race delay clock distribution circuit with skew compensation
US5999032A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Mar 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual phase synchronous race delay clock circuit that will create an internal clock signal in an integrated circuit that is synchronized with and has minimum skew from an external system clock signal is disclosed. The synchronous race delay circuit has an input buffer circuit to receive, buffer, and amplify an external clock signal. The input buffer circuit has a delay time that is the first delay time. A fast pulse generator is connected to the input buffer circuit to create a fast pulse signal. The fast pulse generator is connected to a slow pulse generator to create a slow pulse signal. The fast pulse generator and the slow pulse generator is connected to a race delay measurement means to determine a measurement of a period of the external system clock by comparing a time difference between the slow pulse signal and a following fast pulse signal. A delay control means is connected to the race delay measurement means to receive the measurement of the period of the external system clock. The delay control means will create a first phase control pulse and a second phase control pulse. A duty cycle synchronizer means is connected to the delay control means to create the dual phases…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.