Defect tolerant binary synchronization mark
US5999110A · kind A · utility
23Cited by
6References
44Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Feb 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/90
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an error tolerant binary encoded synchronization mark concatenated with a known pattern, such as a VFO pattern, comprising an encoded pattern of a fixed plurality of bits, the encoded synchronization pattern being at maximum Hamming distance from the concatenated known pattern for the number of bits in the fixed plurality of bits. The error tolerant synchronization mark may also be concatenated with the VFO pattern seen in reverse, and the synchronization pattern additionally is at maximum Hamming distance from the concatenated known VFO pattern seen in reverse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.