Segmented DAC using PMOS and NMOS switches for improved span
US5999115A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Apr 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/765
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital-to-analog converter with cascaded coarse and fine resistor divider strings. The fine resistor string contains 2.sup.N or more resistor segments controlled by N number of fine divider control bits. Resistors located at each end of the fine divider string are a fraction of the nominal value for the remaining fine divider resistor segments. The on-resistance of switches coupling the coarse and fine resistor divider strings is less than or equal to a predetermined fraction of the nominal value for the fine divider resistor segments to minimize contributions to linearity error. The DAC uses all CMOS devices including NMOS and PMOS switches which utilize approximately the full rail-to-rail voltage of the voltage source without the use of additional amplifiers. The DAC provides linearity of about one-fourth LSB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.