System and method for data multiplexing within geometry processing units of a three-dimensional graphics accelerator
US5999196A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Jul 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A 3-D graphics accelerator which includes a command block or preprocessor, a plurality of floating point processors or blocks, and one or more draw processors or blocks. The 3-D graphics accelerator includes a plurality of direct data channels or point-to-point buses, collectively referred to as the CF bus, which connect the command preprocessor to each of the plurality of floating point processors. The 3-D graphics accelerator also includes a plurality of direct data channels or point-to-point buses, collectively referred to as the FD bus, which connect the plurality of floating point processors to each of the draw processors. The system of the present invention also implements a bus from the command preprocessor directly to the draw processors, referred to as the CD bus, which uses portions of the above direct data channels. The CD bus shares or "borrows" the data lines from the CF bus and the FD bus and uses the floating point processors as buffer chips. This allows implementation of a "logical" bus while using existing bus lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.