Non-sequential fetch and store of XY pixel data in a graphics processor
US5999199A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Nov 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes a memory control logic which determines whether fetch and store requests by the graphics processor crosses an X boundary in the internal SRAM devices. If a fetch or store request crosses an X boundary, the memory control logic divides the access into two separate accesses which are then non-sequentially accessed during a single data request cycle. By non-sequentially fetching and storing data, the graphics processor is able to execute a single X crossing for multiple Y scan-line operations to fetch or store data internally.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.