Invertor with suppression of interference currents
US5999427A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Jul 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/49
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An invertor (15) includes a plurality of invertor bridges (B1, . . . ,B8), which are connected in parallel and whose output voltages are summed via a transformer (19). The transformer (19) has a number of primary windings (P1, . . . ,P8) and associated secondary windings (S1, . . . ,S8) which corresponds to the number of invertor bridges (B1, . . . ,B8). Each invertor bridge (B1, . . . ,B8) is connected on the output side to one of the primary windings (P1, . . . ,P8), and the secondary windings (S1, . . . ,S8) are connected in series to sum the output voltages. The transformer (19) has a center tap (23) which is grounded via a ground connection (24). Tertiary windings (T1, . . . ,T8) are assigned to the primary windings (P1, . . . ,P8) and to the secondary windings (S1, . . . ,S8). The tertiary windings (T1, . . . ,T8) are also connected to a common-mode filter (51). The common-mode filter (51) is tuned to common mode interference voltages associated with in-phase or common-mode interference currents flowing via the ground connection (24). Thus, a circuit is formed that attenuates or suppresses the in-phase or common-mode interference currents and the associated interference volta…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.