Low-voltage triple-well non-volatile semiconductor memory
US5999443A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Apr 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new structure of a triple-well non-volatile semiconductor memory cell array and a method of fabricating the memory arrays are described. The circuit layout of the memory array not only includes the conventional floating gates, control gates, cell sources and cell drains, but also adds the local source regions to increase the coupling ratio. Besides, the new design can reduce the number of contact windows, further increasing the packing density of the memory array. The key point of the method is the triple-well formation inside the silicon substrate that lowers the operational voltage of periphery circuit. Furthermore, there are two additional isolation regions between two adjacent metal lines, which can minimize the possibility of cross talk due to shirking spacing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.