Latch circuit, data output circuit and semiconductor device having the circuits
US5999458A · kind A · utility
57Cited by
1References
20Claims
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Assignee
Inventors
Key dates
| Filing date | Jun 19, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Jun 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A latch circuit includes N data latch circuits to which N-bit parallel data are respectively applied where N is an integer, a data input control circuit setting the data latch circuits to a data input state in order, and a data output control circuit which controls the N data latch circuits to output, at different timings, latched data to M output terminals in the order of latch in the N data latch circuits where N.gtoreq.M.gtoreq.1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.