Digital filter system, carrier reproduction circuit using the digital filter system, and demodulation circuit using the carrier reproduction circuit
US5999574A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Mar 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0069
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An input analog signal is sampled at a sampling frequency f.sub.s, which is four times a carrier frequency f.sub.c. A demultiplexer 11 outputs supplied data to four systems sequentially, and generates four zero carriers whose frequencies and amplitudes are equal to each other, with only the phases being different. The delay circuits 12 to 15 delay each one of the zero carriers, and supply delayed signals to adaptive filters 16 to 19. Data output from the four adaptive filters 16 to 19 are selected by a multiplexer 22, and the multiplexer 22 outputs the selected signals as a single signal. The difference between a first zero carrier and an output signals of the first adaptive filter 16 is obtained, and tap coefficients of the adaptive filters 16 to 19 are controlled in accordance with an LMS algorithm based on the difference. A signal output by the multiplexer 22 is output as a reproduced carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.