Dual latch data transfer pacing logic using a timer to maintain a data transfer interval
US5999742A · kind A · utility
2Cited by
22References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1995 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Jan 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual latch character pacing circuit on a semiconductor chip controls data transfer between a pair of microprocessor which have significantly different data transfer rates. A first and second latch are connected in a parallel data path between the two microprocessor. The timing circuit includes a flip-flop which clocks the data between the latches. A one-shot timer is re-started on each transfer of data thereby insuring that the rate of transfer is substantially constant over a character period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.