Method and apparatus for connecting memory chips to form a cache memory by assigning each chip a unique identification characteristic
US6000013A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 15, 1996 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Aug 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention includes a central processing unit (CPU) coupled to a bus. Cache memory devices are coupled to the bus to receive memory requests from the CPU. Each of the cache memory devices includes a cache memory which is coupled to the controller circuit. The controller circuit provides control signals, which enable the cache memory to execute a memory operation requested by the CPU. The controller circuit is coupled to receive predefined address bits comprising memory addresses and memory requests issued by the CPU. Each of the controller circuits disposed in each cache memory device is further coupled to receive an identification number unique to each of the cache memory devices coupled to the bus. The controller circuits disposed in each of the cache memory devices compares the unique identification number with the predefined address bits, such that if the identification number and the predefined address bits match, the controller circuit provides control signals to enable its cache memory to execute the memory operation requested by the CPU at the cache memory location corresponding to the main memory address. In the event the identification does not match the predef…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.