Hybrid tag architecture for a cache memory
US6000017A · kind A · utility
8Cited by
11References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1997 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Aug 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory system having a hybrid tag architecture and a series of data lines is disclosed. The cache memory includes a cache controller and a dirty tag memory included within the cache controller. The dirty tag memory indicates the status of each data line in the cache memory. A tag memory is coupled to the cache controller and is located external to the cache controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.