Method and system for improved power management in information processing system
US6000035A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1996 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Jul 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing system that can reduce the operating frequency of a CPU, or halt the operation of the CPU, at an adequate timing, even when the system is engaged in exchanging data with another independent apparatus (e.g., another PC) via a communication port (a serial port or a parallel port), or when a communication application is being executed. The system has (a) a CPU that operates in a normal mode, in a power saving mode in which less power is consumed than is required in a normal mode, or in a stop mode in which operation is completely halted; (b) at least one peripheral device; (c) a bus employed for communication between the CPU and the peripheral device; (d) a communication port, physically connected to another independent apparatus, for performing data transfer; (e) a bus cycle detector monitoring a bus cycle on the bus; (f) a state detector determining an operational mode of the CPU in response to a detection by the bus cycle of access of the communication port; (g) a signal generator providing, when the state detector ascertains that the operational mode is to be the power saving mode, a control signal to the CPU to set the CPU to the power saving mode; and (…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.