Chip carrier with embedded leads and chip package using same
US6002170A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1996 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Jul 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package includes a flat plate body or carrier with a plurality of leads embedded therein but exposed at the first and second surfaces, e.g., the top and bottom surfaces, of the plate body. The body has a predetermined shape and may include a recess formed in the upper surface of the body to a prescribed depth. A semiconductor chip is mounted on the upper surface of the plate body or carrier. Metallic bonding wires electrically connect the leads of the body with the bonding pads of the chip, and an epoxy molding compound seals a predetermined portion including the chip, the leads, and the metallic wires. A plurality of like chip packages may be vertically stacked. Instead of epoxy molding, a thin lid having leads similarly embedded therein may be attached to the upper surface of the body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.