Clock recovery circuit

US6002279A · kind A · utility

Assignee

• G-2 Networks, Inc. · US

Inventors

• William P. Evans · Catonsville, US
• Eric Naviasky · Baltimore, US
• Patrick Farrell · Baltimore, US
• Anthony Caviglia · Laurel, US
• John Ebner · Baltimore, US
• Hugh Miller Thompson · Houston, US
• Hao Tang · Shanghai, CN

Key dates

• Filing date: Oct 24, 1997
• Grant date: Dec 14, 1999
• Expiry date: Oct 24, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L7/0025
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.