Reconfigurable texture cache
US6002410A · kind A · utility
89Cited by
3References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 25, 1997 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Aug 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable cache in a signal processor provides a cache optimized for texture mapping. In particular, the reconfigurable cache provides two-banks of memory during one mode of operation and a palettized map under a second mode of operation. In one implementation, the reconfigurable cache optimizes mip-mapping by assigning one texture map in one of the memory banks and a second texture map of a different resolution to the other memory bank. A special mapping pattern ("supertiling") between a graphical image to cache lines minimizes cache misses in texture mapping operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.