Semiconductor memory device
US6002606A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 1, 1998 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Dec 1, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor memory device of this invention includes a plurality of blocks and an external bit line extending through the plurality of blocks in a column direction, wherein each of the plurality of blocks includes a plurality of bank regions each including a plurality of memory cells arranged in a matrix, the plurality of bank regions are arranged in the column direction, each of the plurality of blocks has a main bit line, the main bit line of each of the plurality of blocks extends through the plurality of bank regions in the column direction in parallel with the external bit line, to be shared by the plurality of bank regions, and the semiconductor memory device further includes a block selector for receiving a signal from outside for selecting one of the plurality of blocks and activating the main bit line corresponding to the selected block with the external bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.