Clock shift circuit and synchronous semiconductor memory device using the same
US6002615A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mask control circuit for generating an internal mask designation signal for masking read data includes a shift circuit incorporating and shifting an applied signal in accordance with an internal column related clock signal CLKD for transmission and a reset means responsive to inactivation of a clock activation signal defining a generation period of the internal column clock signal for resetting the shift circuit in an initial state. An output from the shift circuit is changed from the initial state to another upon clock reapplication, so that the influence by an internal output signal from the shift circuit in the previous application is eliminated, thereby generating a correct internal mask designation signal. A clock shift circuit capable of reducing current consumption without accompanying any malfunction and a synchronous semiconductor memory device using the same is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.