Method and apparatus of column redundancy for non-volatile analog and multilevel memory
US6002620A · kind A · utility
51Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1998 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Jan 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides column redundancy circuits in a storage array, which circuits are used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The invention includes a scheme to latch and transfer the redundancy information, a redundancy logic circuit, a redundancy column driver, an array architecture with column redundancy, a scheme to program and read the column redundancy memory cells, a scheme to multiplex the fuses, and circuits to use an out-of-bound address as a column redundancy enable/disable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.