Performance optimizing compiler for building a compiled SRAM
US6002633A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1999 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Jan 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compiler for building at least one compilable SRAM including at least one compilable sub-block. A global control clock generation circuit generates a global control signal. At least one local control logic and speed control circuit controls the at least one compilable sub-block. The local control logic and speed control circuit is controlled by the global control signal. An algorithm receives an input capacity and configuration for the sub-block of the SRAM array. An algorithm determines a number of wordlines and bitlines required to create the sub-block of the input capacity. An algorithm optimizes a cycle time of the sub-block by determining global control clock circuits based upon the number of wordlines and bitlines in the sub-block. An algorithm optimizes access time of the sub-block by determining local speed control circuits based upon the number of wordlines and bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.