Apparatus and methods for performing arithimetic operations on vectors and/or matrices
US6003058A · kind A · utility
8Cited by
3References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1997 |
| Grant date | Dec 14, 1999 |
| Priority date | — |
| Expiry date | Sep 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply-multiply-accumulate (MMA) system (10) efficiently evaluates matrix products X=F*C. Matrix C is dissected into submatrices A and B taking advantage of symmetry in C. LOG unit (14) converts B, A, and F to LOG values B', A' and F'. These are summed in K parallel calculating units CU's (18) and converted back to Normal domain as P=F*B*A in ALOG units (22) and sent to accumulators ACU's (24). The ACU's (24) accumulate the results. An output buffer (26) combines the results. The B', A' values (32,34) are held in a cache memory (20) and the LOG sums are performed in two steps with intermediate storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.