Method for manufacturing MOS device with adjustable source/drain extensions
US6004851A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1998 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Mar 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a metal-oxide-semico nductor field effect transistor (MOSFET) having a drain and a source each of which has a lightly doped area, an enhanced lightly doped area and a heavily doped area is disclosed. The method includes steps of lightly doping the silicon substrate having a gate structure to form the lightly doped areas of the source and the drain; forming a first non-conductive layer covering the silicon substrate and the gate, forming a second non-conductive layer covering the first non-conductive layer, forming a duple-sidewall including a side-wall-spacer of the first non-conductive layer and an inner spacer, heavily doping the silicon substrate to form the heavily doped areas of the source and the drain respectively, removing the side-wall-spacer of the first non-conductive layer, executing an anisotropic etching on the inner spacer to form a cascade-shaped spacer of the gate, and doping the silicon substrate to form the enhanced lightly doped area and thus forming the extension area of the heavily doped area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.