Semiconductor integrated circuit device having wiring layout for small amplitude signals
US6005265A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1997 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Sep 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device capable of reducing delay of wiring as far as possible is provided. The semiconductor integrated circuit device comprises at least two sets of pairs of signal lines having first polarity and second polarity opposite thereto, wherein the signal line of the first polarity of the signal lines of the second set is disposed at the portion adjacent to the signal line of the first polarity of the signal lines of the first set, the signal line of the second polarity of the first set is disposed at the portion adjacent to the signal line of the first polarity of the second set, and the signal line of the second polarity of the second set is disposed at the portion adjacent to the signal line of the second polarity of the first set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.