Package for semiconductor device laminated printed circuit boards
US6005289A · kind A · utility
17Cited by
0References
5Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Oct 24, 1996 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Oct 24, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The minimum spacing between wires disposed on a printed circuit board of a printed circuit board ball grid array package is reduced. Wiring layers are narrower than in the prior art because they are not plated and because only one metal layer is plated on the wiring layers. The narrower wiring layers can be formed easily with small spaces between wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.