AGP/DDR interfaces for full swing and reduced swing (SSTL) signals on an integrated circuit chip
US6005412A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1998 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Apr 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4077
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An I/O interface includes latches, clocks, and conditioning circuits implemented in a custom physical layout to produce a reliable and flexible interface to high frequency busses running a plurality of protocols and signal specifications. Three clock trees are used to synchronize the buffering and conditioning of input/output signals before sending such signals to a pad or core. The clock trees are implemented via custom layouts to allow tight control of clock/strobe parameters (e.g., skew, duty cycle, rise/fall times). Two of the clock trees are local to the I/O interface and trigger a plurality of output latches configured on-the-fly to buffer output data signals from the core in asynchronous or synchronous mode. In the synchronous mode, a clock/strobe could be either edge-centered or window-strobe with respect to the data. The third clock tree distributes clock/strobes from an external source and is used to trigger a plurality of input latches configured on-the-fly to buffer input data from the pad in either a window-strobe mode or an edge-centered mode. The I/O interface also includes conditioning circuits that condition the I/O signals to be compliant with AGP/DDR protocols, a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.