Digital PLL circuit
US6005427A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 22, 1996 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Oct 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0994
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a digital PLL circuit, a DCO 3a comprising a full adder 33 and a delay circuit 34 accumulate a frequency control data N, to generate digital phase data ACC which periodically changes at a rate corresponding to the frequency control data N, a latch circuit 11 latches the digital phase data ACC with the aid of an input digital signal .phi..sub.in, and outputs it as a digital phase difference signal PC, and a loop filter 2 removes components in an unwanted frequency band from the digital phase difference signal PC, to form the frequency control data which is applied to the digital control oscillator means. In the digital PLL circuit, the digital phase data ACC itself, being synchronized in phase with the input digital signal .phi..sub.in, is periodically changed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.