Channel quality circuit employing a test pattern generator in a sampled amplitude read channel for calibration
US6005731A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 1997 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Apr 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/182
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlatio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.