Floating gate content addressable memory
US6005790A · kind A · utility
38Cited by
5References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1998 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Dec 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile storage device storing a data bit received from a bitline via an accessing circuit. A coupling circuit couples either the bitline, or a complementary bitline to a biasing circuit dependent on the logic level of the data bit stored in the storage device. The biasing circuit generates a match signal when a data bit having the same logic level as the stored data bit is applied to the bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.