Bank selectable Y-decoder circuit and method of operation
US6005822A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1998 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Dec 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Bank selectable Y-decoder circuit (24) generates a plurality of Y-select signals (60, 62, 64, 66) for addressing columns of a plurality of memory banks (12, 14) in a memory array (10) and includes a high-order column factors decode circuit (34) for receiving a plurality of column factor signals. A first low-order column factor circuit (30) generates a first set of Y-select signals (60, 62) for addressing at least one column of a first set of memory banks (12). A second low-order column factors circuit (32) generates a second set of Y-select signals (64, 66) for addressing at least one column of a second set of memory banks (14). The result is a Y-decoder circuit (24) that consumes less silicon die area, without a reduction in circuit performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.