Method and device for synchronizing digital decoder and encoder clocks
US6005872A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1996 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Jul 17, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/44004
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to a method of synchronization of clocks wherein, in a system including a digital decoder of a receiver equipped with a sampling clock and a digital encoder of an transmitter also equipped with a sampling clock, said method includes the following stages: in the transmitter, coding by packets of samples of a signal by time intervals of predetermined duration and triggering of the transmission of a data frame when a packet of data is ready to be sent; in the receiver, detection of start of said frame, and generation of a reference signal following said detection, said reference signal being used to correct the clock of the receiver. Another object of the invention is a method of synchronization of clocks wherein, in a system including a digital decoder of a receiver equipped with a sampling clock and a digital encoder of a transmitter also equipped with a sampling clock, in which the transmitter sends frames containing data packets corresponding to a number known of samples, said method includes the following stages in the receiver: reception of a data frame including a packet of data, decoding of said packet and writing of the decoded data in a memory, reading…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.