Method for providing offset mask for pseudo-noise sequence generator

US6005888A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventor

• Kenneth S. Barron · Plano, US

Key dates

• Filing date: Jul 8, 1997
• Grant date: Dec 21, 1999
• Expiry date: Jul 8, 2017

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2207/583
• WIPO field: Telecommunications
• WIPO sector: Electrical engineering

Abstract

A method, executed in a microprocessor, for providing a shift-and-add mask, M=m.sub.1, m.sub.2, . . . , m.sub.N-1, m.sub.N, for a pseudo-noise sequence generator ("PNSG"). The PNSG generates a first pseudo-noise ("PN") code, and has N stages, each stage being at one of two states. The PNSG also has an associated shifter for generating a shifted PN code which is the same code as the first PN code, but delayed by K chips. The shifted PN code is generated as the inner product of the shift-and-add mask with the states of the stages of the PNSG. According to the inventive method, a value of K is provided, and it is determined whether K is 0. If K is 0, M is provided such that m.sub.N =1 and, for all n.noteq.N, m.sub.n =0. However, if K is not 0, it is determined whether K is greater than N. If K is greater than N, the remainder, R, of the division D.sup.K-1 /f(D), is determined, where EQU D.sup.K-1 =(m.sub.1 c.sub.1 +m.sub.2 c.sub.2 + . . . +m.sub.N c.sub.N)+(m.sub.2 c.sub.1 +m.sub.3 c.sub.2 + . . . +m.sub.N c.sub.N-1)D+(m.sub.3 c.sub.1 +m.sub.4 c.sub.2 + . . . +m.sub.N c.sub.N-2)D.sup.2 + . . . +m.sub.N c.sub.1 D.sup.N-1, and EQU f(D)=c.sub.1 D.sup.N +c.sub.2 D.sup.N-1 + . . . +c.sub.N…