Method and apparatus for adaptable burst chip select in a data processing system
US6006288A · kind A · utility
8Cited by
9References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 6, 1996 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Jun 6, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system (20) having a burst address generator (BAG) 55, with a programmable transaction mode applicable to both cache and pre-fetch architecture types. BAG 55 asserts a data acknowledge (DTACK) signal to end a burst transfer on either a physical boundary, as in pre-fetch mode at the end of a row in a memory device, or a limit detection, as in cache mode where the limit is determined by the length of a cache line. BAG 55 increments the burst address internally, and for operations in pre-fetch mode, the user determines if the incremented address is provided external to data processor (22).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.