Coprocessor system for accessing shared memory during unused portion of main processor's instruction cycle where main processor never waits when accessing shared memory
US6006319A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Mar 20, 1996 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Mar 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A coprocessor system is disclosed in which a CPU in a game machine body and a CPU in a game cartridge are formed by CPU cores having the same architecture and memory mapping functions. The cycle time of a second CPU, for example the CPU in the game cartridge, is shorter than the cycle time of the first CPU, for example the CPU in the game machine body. The first CPU accesses memory during a first time period that is longer than the program memory access time but shorter than the first CPU cycle time. The second CPU accesses the program memory during a second time period, which is the time difference between the end of the first time period and the end of the first CPU's cycle time. The second CPU may also access the program memory during the first time period if no first CPU memory access is pending. Since the first CPU's memory access during the first time period has priority over the second CPU's, the first CPU never waits to access shared memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.