Apparatus for restraining over-eager load boosting in an out-of-order machine using a memory disambiguation buffer for determining dependencies
US6006326A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for restraining over-eager boosting of load instructions past store instructions in an out-of-order processor. The system comprises a memory disambiguation buffer for storing load and store instruction addresses and associated data and an instruction scheduling window in operative association with the memory disambiguation buffer. The instruction scheduling window and the memory disambiguation buffer determine load/store dependencies and effectuate replay of the store and load instructions wherein a dependent load instruction has been executed prior to a store instruction. An instruction cache is provided in operative association with the memory disambiguation buffer, together to associate the dependent load instructions with a store instruction such that the store instruction is subsequently executed prior to the dependent load instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.