Communication interface between two finite state machines operating at different clock domains
US6006340A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | Dec 21, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for creating a communication interface between a first finite state machine, operating in accordance with a write side clock in a write side clock domain, the first finite state machine operating to generate a Request signal for a transaction and for requesting the transfer of information associated with the Request signal, and a second finite state machine, operating in accordance with a read side clock in a read side clock domain at a different frequency than the write side clock, comprising: a register file; a first interface to the first finite state machine; a second interface to the second finite state machine; and logic for loading in accordance with the write side clock, a communication queue of the information into the register file in accordance with the Request signals from the first finite state machine, for reading by the second finite state machine via the second interface in accordance with the read side clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.