Differential CMOS logic family
US6008670A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1997 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Aug 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a differential CMOS cell that achieves faster switching speeds than conventional CMOS logic by 1) biasing a differential pair of output nodes to a relatively high logic low voltage threshold, and 2) pulling up the differential pair of output nodes to a logic high voltage level. The differential CMOS cell is designed such that the difference between logic low and logic high voltage thresholds is much less than in traditional CMOS circuits (i.e., approximately 0.8 V-1.0 V as compared to 2.6 V). A lower voltage swing allows for fast switching of a differential output signal. In a preferred embodiment, the differential CMOS cell receives a primary differential input signal, and respective first and second secondary differential input signals. The differential CMOS cell includes a differential pair of arm circuits, each comprising a primary input switch for receiving a component of the primary differential input signal, and a differential pair of secondary input switches for receiving either the first or second secondary differential input signal. Each arm circuit is coupled between a current source and a voltage source. In operation, the primary differential input s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.